1. Field of the Invention
The present invention relates to a semiconductor device and, for example, relates to a semiconductor device having a mechanism for reinforcing a multilayer interconnection structure.
2. Related Art
In recent years, with ever higher degrees of integration and higher performance of semiconductor integrated circuits (LSI), new microprocessing technologies have been developed. In particular, to achieve an ever faster speed of LSI, there has been a growing trend recently to replace the conventional wire material of aluminum (Al) alloys with copper (Cu) or Cu alloys (hereinafter, called Cu together) having lower resistance. Since it is difficult to apply the dry etching method, which is frequently used for forming an Al alloy wire, to Cu for microprocessing, the so-called damascene process is mainly adopted for Cu, in which a Cu film is deposited onto a dielectric film to which groove processing has been provided and then the Cu film is removed except in portions where the Cu film is embedded inside a groove by chemical-mechanical polishing (CMP) to form an embedded wire. Further, when multilayer Cu interconnection should be formed, particularly a wire formation method called a dual damascene structure may be used. According to the method, a dielectric film is deposited onto a lower layer wire and predetermined via holes and trenches for upper layer wire are formed, and then Cu to be a wire material is embedded in the via holes and trenches simultaneously and further unnecessary Cu in the upper layer is removed by CMP for planarization to form an embedded wire.
Recently, the use of a low dielectric constant film (low-k film) having a low relative dielectric constant as an inter-level dielectric is studied. That is, an attempt is made to reduce parasitic capacitance between wires by using a low dielectric constant film (low-k film) whose relative dielectric constant k is 3.4 or less, instead of a silicon oxide (SiO2) film whose relative dielectric constant k is about 4.1.
Here, a low dielectric constant film is formed by reducing the density of material thereof or eliminating polarity in the material. For example, to reduce the density of material, the material is commonly made porous. Thus, a low dielectric constant film has a low density and commonly has low values of mechanical physical properties such as the Young's modulus. That is, the material itself of a low dielectric constant film has low strength. In addition, a low dielectric constant film has a film structure of low polarity to reduce the dielectric constant in the film. Thus, adhesion density at a lamination interface of a laminated film in which low dielectric constant films or a low dielectric constant film and other films are laminated is weak. More specifically, the material of film deteriorates due to penetration of a gas used for forming a via hole or a trench in the low dielectric constant film, working processes or the like. Thus, mechanical strength of the material itself of a low dielectric constant film may be degraded or adhesion strength at an interface of a laminated film including a low dielectric constant film may be degraded.
Weaknesses of film strength of low dielectric constant films and those of adhesion strength at the interface of laminated films including a low dielectric constant film produce a big bottleneck particularly in a multilayering process in which wires in a semiconductor device are formed into a multilayer structure. To eliminate the bottleneck, an attempt is made to improve reliability by arranging dummy wires as reinforcing materials in a low dielectric constant film.
Defects resulting from weaknesses of film strength of low dielectric constant films and those of adhesion strength at the interface of laminated films including a low dielectric constant film specifically include short-circuit defects due to dielectric breakdown around a via in a heat process such as sintering, interface peeling defects in the CMP process, dielectric breakdown under padding during bonding or probing, chipping during dicing, and dielectric interface peeling during a reliability test (such as TCT) after packaging.
Arrangement of dummy wires around effective wires has been effective in reliability improvement for short-circuit defects due to dielectric breakdown around a via in a heat process such as sintering, interface peeling defects in the CMP process, and dielectric breakdown under padding during bonding or probing. For chipping during dicing and dielectric interface peeling during a reliability test (such as TCT) after packaging, that is, dielectric peeling defects starting from a chip end, measures to control dielectric peeling defects starting from a chip end have been taken by arranging a via ring or dummy wire on a scribe line and in an area between the scribe line and an area where effective wires are arranged in the chip (See Published Unexamined Japanese Patent Application No. 2005-229086 (JP-A-2005-229086), for example).
In recent years, with an increasingly lower dielectric constant of inter-level dielectric of LSI and lower mechanical strength involved therein, the coverage factor in a chip of a via ring or dummy wire arranged on a scribe line and in a boundary part between the scribe line and an area where effective wires are arranged in the chip is becoming increasingly higher and a structure thereof more complex. More specifically, a via ring arranged at a boundary part between an effective wiring area and a scribe line assumes the role of suppressing penetration of moisture content or development of cracks from a chip end, and the via ring is formed, for example, from a wiring structure arranged like surrounding the effective wiring area ranging from the bottom Cu wiring layer to the top Cu wiring layer or an electrode pad thereon and a wall-shaped via structure connecting these layers vertically (See Published Unexamined Japanese Patent Application No. 2005-142553 (JP-A-2005-142553), for example). At least one via ring (one structure) is arranged in a boundary part between an effective wiring area and a scribe line toward and outer periphery. The number of via rings increases with an increasingly lower dielectric constant of dielectric film and lower mechanical strength involved therein, and even as many via rings as 10 may be arranged. Such an increase in the number of via rings reduces a substantially effective wiring area in the chip, posing a problem for still higher integration.
The structure of a dummy wire arranged on a via ring or scribe line is becoming more complex such as a shape in which a plurality of cylindrical vias or wall-shaped vias is connected to one wire and also the coverage factor is becoming higher. This is intended to suppress development of cracks from a chip end and, in the meantime, a new problem resulting from more complex shapes arises. If a wire of metal such as Cu is formed in a dielectric film, a difference of the coefficient of linear expansion between the dielectric film and wire material causes thermal stress at a dielectric film/wire interface during a heat process. In a dummy wire having the above complex shape and formed on a via ring or scribe line, the thermal stress is likely to become larger than that in an effective wiring area. This thermal stress causes no problem when the dielectric film has sufficient mechanical strength, but if a via ring or dummy wire having a complex shape and a high coverage factor is arranged in a low dielectric constant film having low mechanical strength, there is a danger that dielectric film cracks may arise due to thermal stress caused at a dielectric film/wire interface during a heat process. That is, a via ring or dummy wire arranged to control cracks from a chip end itself is likely to become a starting point of dielectric film cracks as the shape thereof becomes more complex and the coverage factor becomes higher.
In a semiconductor device using a low dielectric constant film as inter-level dielectric, as described above, a dummy wire on a via ring or scribe line causes a bottleneck in higher integration and it is very likely that dielectric film cracks starting from the dummy wire on the via ring or scribe line occur during a thermal process. Thus, it is very likely that a fatal defect is caused in semiconductor devices or fabricating processes thereof. That is, it is likely that performance or quality of semiconductor devices deteriorates, leading to lower reliability of semiconductor devices. At the same time, it is likely that yields of semiconductor devices drop with defective semiconductor devices being manufactured, leading to lower production efficiency of semiconductor devices.